[Libre-soc-bugs] [Bug 412] set up litex for peripherals and linking to core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=412

--- Comment #10 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
It's possible to plug your CPU to LiteX without modify LiteX itself, to so do,
you could have a look at https://github.com/enjoy-digital/litex_vexriscv_smp
and see how the CPU wrapper/software is created in the vexriscv_smp repository.

You can also look at
https://github.com/enjoy-digital/litex_vexriscv_smp/blob/master/sim.py for a
Verilator simulation. (capable of loading binaries and booting linux in the
case of VexRiscv SMP).

That will probably be easier for you to develop like this, this will avoid
forking LiteX. Once you have something that compiles correctly with Verilator
(just execute sim.py on the case of VexRiscv SMP), I could help you getting
this running if this is not already the case. (You can add --trace to the
simulation to generate the waveform).

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