[Libre-soc-bugs] [Bug 412] set up litex for peripherals and linking to core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=412

--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
florent, i think it is possible to literally copy minerva cpu_params, the full
set of ibus and dbus names exactly the same, but removing interrupts (for now).

and i believe this should do the trick of allowing the core to start running
immediately from the default pc=0

    self.cpu_params = dict(
          i_go_insn_i = 1
     )

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