[Libre-soc-bugs] [Bug 412] set up litex for peripherals and linking to core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=412

--- Comment #7 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
> To be able to do the LiteX integration and use the different features i need from you:
> - the nmigen command to run to generate the top level of the CPU (is it what test_issuer is doing?)

yes, although it spews additional debug output at the moment.  let us instead
go with "soc/simple/issuer_verilog.py filename.v"

(done)
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/issuer_verilog.py;hb=HEAD

> - a description of the different signals of the CPU and the ones mandatory/ the ones optional.

ibus__*
dbus__*

these should be exactly as in Minerva: i really did copy the code as-is (except
to make it 64 bit)

hmm however it seems i have some additional signals that get it "going".  a
sort-of debug interface, these are, mandatory:

* go_insn_i

these are optional:

* pc_i
* pc_i_ok
* core_start_i
* core_stop_i
* core_bigendian_i
* halted_o
* busy_o

> - the example you already simulated with the RAM and code from Microwatt.

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/test/test_microwatt.py;hb=HEAD#l40

line 40 is where the unit test is added to the list of binaries to run.

line 89 shows how to kick it out of "halted"

lines at 119 show how to set the pc externally.  it defaults to zero including
after reset so this is not strictly necessary.

lines at 124 show how to kick it into running instructions.  go_insn_i setting
to 1 is mandatory


when we have a "proper" debug interface (JTAG, other) this will be a little
different

if you can help get us started i can send you patches.

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