[Libre-soc-bugs] [Bug 417] FSM-based ALU example needed (compliant with ALU CompUnit)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=417

--- Comment #21 from Cesar Strauss <cestrauss at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #20)
> > Unit tests sample their signals just before the previous clock rising edge,
> interesting that it is just *before* the rising edge.  i always thought it
> was "on" (or "just after").

You are right, actually.

Unit test sample their signals just after the clock rising edge.

Sorry for the confusion.

The revised reasoning is:

As the state register is updated to the "DONE" state, done_o is asserted.

However, this occurs a few nanoseconds after the rising edge. By that time, the
unit test already sampled valid_o, which was still zero then.

So, there will be a full clock cycle where valid_o is high and ready_i is also
high.

On the next cycle, two things happen:

1) The FSM notices that ready_o was high on the last cycle, and goes to "IDLE",
negating valid_o. Again, this takes a few nanoseconds.
2) The unit test notices that valid_o was still high at the clock rising edge,
and negates ready_i.

I hope this explains better what is going on at the unit test and the FSM.

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