[Libre-soc-bugs] [Bug 417] FSM-based ALU example needed (compliant with ALU CompUnit)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=417

--- Comment #20 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #19)

> Unit test works sequentially, not combinatorially, unless Settle() is used.

we have encountered situations where it is needed.  i do not know why.

> This unit test does not uses Settle().
> 
> Unit tests sample their signals just before the previous clock rising edge,

the key word being "samples".

interesting that it is just *before* the rising edge.  i always thought it was
"on" (or "just after").


> much like registers. ready_i was held high for the full clock cycle, before
> the unit test could notice that valid_i was asserted on that cycle.

okaay.  then please do remove that extra yield.

> An extra clock cycle (yield) is not needed. The unit test, as written, is
> correct.

ok.  this is good.  then the bug is akmist certainly in cxxsim.

l.

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