[Libre-soc-bugs] [Bug 417] FSM-based ALU example needed (compliant with ALU CompUnit)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=417

--- Comment #19 from Cesar Strauss <cestrauss at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #15)
> ok so this is just what it took to "fix" the problem in cxxsim.  
> 
>                  m.d.comb += self.n.valid_o.eq(1)
>                  with m.If(self.n.ready_i):
>                     # go back to IDLE when the data is accepted
>                     m.next = "IDLE"
> 
> this *should* set the FSM to "IDLE" on the *next* cycle, however
> the fact that in the unit test ready_i is dropped *immediately*,
> combined with the fact that valid_o is set combinatorially, what
> happens instead is:
> 
> * valid_o is set to 1 (combinatorially)
> * unit test (combinatorially) notices that (in the while yield loop)
> * unit test (combinatorially) sets ready_i to 0
> * DUT - *combinatorially* - notices that ready_i has been set to 0
> * DUT *NO LONGER ASSERTS m.next=IDLE*

Unit test works sequentially, not combinatorially, unless Settle() is used.

This unit test does not uses Settle().

Unit tests sample their signals just before the previous clock rising edge,
much like registers. ready_i was held high for the full clock cycle, before the
unit test could notice that valid_i was asserted on that cycle.

An extra clock cycle (yield) is not needed. The unit test, as written, is
correct.

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