[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #16 from Jean-Paul.Chaput at lip6.fr ---
(In reply to Luke Kenneth Casson Leighton from comment #15)
> jean-paul, i see you're back from holiday in the rainy lovely beaches.

  Sadly, yes.

> i have pushed a couple of updates to test_issuer.il one of which added (then
> removed) the div unit.  i also, back in issuer.py, provided an option in the
> code to add pipeline types, so mul can be added etc. by changing one line.
> 
> you will need to git pull all soc repositories however *do not* update
> nmigen right now as there are issues outstanding with it.

  Maybe too late, I just did it a couple of days ago. But I can easily
  roll back if you give me a commit hash to stick to.

> i would if there is time very much like to do at least a top level
> hierarchical layout, regardless but also because there will be space unused.
> 
> the reason is that when it comes to showing people the layout, it is
> possible to point and say, "this is the Logical pipeline" and so on.

  I understand very well, it makes much easier to comment layout,
  but maybe not the most efficient.

> to help with that, i would like to be able to set the width but not height
> or height but not width when doing the area calculation.
> 
> what can then be done is:
> 
> * run all pipeline layouts with the exact same height (large height)
> 
> * get a series of varied widths back for each pipeline (some of them will be
> very thin, some like MUL will be fat)
> 
> * lay them out in a row
> 
> * have the regfiles below them, placed optimally closest to the pipelines
> that need them
> 
> based on the widths of the pipelines and the widths of the regfiles it may
> even be practical to use an algorithm that works out the shortest paths, in
> 1D.

  Making blocs with fixed height or width is easy. The problems lays in
  the top assembly. In ASIC terminology, it's the floorplan (Placement of
  the top level blocks). Coriolis has no real support for that yet.

  To achieve that quickly we may try to create blocks that are directly
  connectable side by side. Meaning that the connectors are exactly at
  the same position & layer on each sides of both blocks. This is ok for
  2 pins nets, but if there are more, we have to route though a block a
  net (it can be done with minimum fuss also).

  Normally we should use a block & channel routing (routing space between
  the blocks).

> what's your thoughts, is this reasonable?

  I will try a first flat run to get a feel about runtime and memory size.
  Then I will see if we must break it. Note that, the ASIC IBM benchmarks
  supplied for the ISPD contest are completely flat (no block whatsoever,
  up to 1 million gates).

> then also this would help identify the areas which are not routing, because
> it is less gates.  also it would speed up layout time.

  breaking the design in smaller block would certainly reduce the P&R time
  and help solve problem one block at a time. As Staf did put some time ago,
  for big ASICs, the maximum run time should be "one night".

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