[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #15 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
jean-paul, i see you're back from holiday in the rainy lovely beaches.

i have pushed a couple of updates to test_issuer.il one of which added (then
removed) the div unit.  i also, back in issuer.py, provided an option in the
code to add pipeline types, so mul can be added etc. by changing one line.

you will need to git pull all soc repositories however *do not* update nmigen
right now as there are issues outstanding with it.

i would if there is time very much like to do at least a top level hierarchical
layout, regardless but also because there will be space unused.

the reason is that when it comes to showing people the layout, it is possible
to point and say, "this is the Logical pipeline" and so on.

to help with that, i would like to be able to set the width but not height or
height but not width when doing the area calculation.

what can then be done is:

* run all pipeline layouts with the exact same height (large height)

* get a series of varied widths back for each pipeline (some of them will be
very thin, some like MUL will be fat)

* lay them out in a row

* have the regfiles below them, placed optimally closest to the pipelines that
need them

based on the widths of the pipelines and the widths of the regfiles it may even
be practical to use an algorithm that works out the shortest paths, in 1D.

what's your thoughts, is this reasonable?

then also this would help identify the areas which are not routing, because it
is less gates.  also it would speed up layout time.

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