[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #17 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #16)
> (In reply to Luke Kenneth Casson Leighton from comment #15)

>   I understand very well, it makes much easier to comment layout,
>   but maybe not the most efficient.

not a problem, this is a test chip.



> > based on the widths of the pipelines and the widths of the regfiles it may
> > even be practical to use an algorithm that works out the shortest paths, in
> > 1D.
> 
>   Making blocs with fixed height or width is easy. 

> The problems lays in
>   the top assembly. In ASIC terminology, it's the floorplan (Placement of
>   the top level blocks). Coriolis has no real support for that yet.

that's ok.  the alu16 example showed how to do it.

what i do not want, is, to have different width and height pipelines, which if
we add even just one new function to one pipeline the entire layout must be
redone.

the current system, you call a function and it tells you the width *and* height
estimate needed to route that block, and they are squares (appx).

i would like the estimate system to be able to set a fixed height, and it to
tell me the width.

then the placement of all pipelines cab be lined up.

the inputs and outputs will all be on one side (SOUTH) to connect to register
files.


>   To achieve that quickly we may try to create blocks that are directly
>   connectable side by side.

ok so the pipelines except for LDST have *ZERO* connectivity to anything other
that the register file Buses.

this is a VERY deliberate hard rule that has been set.

there is NO interconnection between pipelines.

therefore the floorplan is:

* pipelines in a row at the top
* Register Buses and "Priority Pickers" in the middle
* Register Files at the bottom
* Decoder to the side, connected to the Fast Regfile (to get the Program
Counter).

so it is very regularly organised.

therefore for most Regfiles, all the ports can be NORTH.

> Meaning that the connectors are exactly at
>   the same position & layer on each sides of both blocks. This is ok for
>   2 pins nets, but if there are more, we have to route though a block a
>   net (it can be done with minimum fuss also).

the only one which might need pins on different sides is FAST Regs because it
contains the Program Counter, the MSR (sets 64 bit mode, User mode, LE/BE etc).

oh, and LDST of course, the memory connection comes out NORTH but registers are
SOUTH.

everything else is extremely regular.

>   Normally we should use a block & channel routing (routing space between
>   the blocks).

nice.

> > what's your thoughts, is this reasonable?
> 
>   I will try a first flat run to get a feel about runtime and memory size.
>   Then I will see if we must break it. Note that, the ASIC IBM benchmarks
>   supplied for the ISPD contest are completely flat (no block whatsoever,
>   up to 1 million gates).

mad :)

well given that there are things to fix i would prefer that you are able to run
and debug on a fast loop.

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