[Libre-soc-bugs] [Bug 324] create POWER DIV pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #57 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #56)
> (In reply to Jacob Lifshay from comment #53)
> > it will output (last output line split over two lines:
> > {"rt":"0x0"}
> > {"rt":"0x0","so":true,"ov":true,"ov32":true}
> > {"rt":"0x0","cr0":{"lt":false,"gt":false,"eq":true,"so":false}}
> > {"rt":"0x0","so":true,"ov":true,"ov32":true,
> > "cr0":{"lt":false,"gt":false,"eq":true,"so":true}}
> 
> ah this is _really_ useful as it helps check the output regspec allocations
> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/alu/pipe_data.py;
> hb=HEAD

I manually entered the output regs for each instruction, so I'm much more
likely to have accidentally missed an output than if you use the csv files we
derived from a working core.

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