[Libre-soc-bugs] [Bug 324] create POWER DIV pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #56 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #53)
> (In reply to Luke Kenneth Casson Leighton from comment #48)
> > (In reply to Jacob Lifshay from comment #44)
> > > (In reply to Luke Kenneth Casson Leighton from comment #41)
> > > > btw jacob i noticed that on qemu, divw sets RT=RA when RB=0.
> > > > 
> > > > can you check that behaviour on POWER9?
> > > 
> > > IIRC, on POWER9, division by zero results in RT=0 for all div*/mod*
> > > instructions. I specifically included that as a test case in
> > > power-instruction-analyzer since that's a case where the result is undefined
> > > according to the PowerISA spec. For divwo, see:
> > > https://salsa.debian.org/Kazan-team/power-instruction-analyzer/-/blob/
> > > 13dae100c6bc5685059195010ceb46ae68b9f306/src/instr_models.rs#L153
> > 
> > qemu definitely sets RT=RA for divw when RB=0.  note: not divwo - *divw*.
> > 
> > which is why i asked if you could check.  hugh and paul mackerras mentioned
> > that this *might* have been old behaviour on e.g. POWER7 or POWER8.
> 
> I just updated power-instruction-analyzer to include all div*[o][.]
> variants, they all match the original instr_models.rs -- all of `divw`,
> `divwo`, `divw.`, and `divwo.` all provide the exact same results when
> tested on POWER9.

ah fantastic.  this is really helpful 

> So, unless we made a mistake somewhere, qemu doesn't match POWER9's behavior
> (which is to be expected, since that part is undefined).

still annoying though as it means manual checking
> it will output (last output line split over two lines:
> {"rt":"0x0"}
> {"rt":"0x0","so":true,"ov":true,"ov32":true}
> {"rt":"0x0","cr0":{"lt":false,"gt":false,"eq":true,"so":false}}
> {"rt":"0x0","so":true,"ov":true,"ov32":true,
> "cr0":{"lt":false,"gt":false,"eq":true,"so":true}}

ah this is _really_ useful as it helps check the output regspec allocations
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/alu/pipe_data.py;hb=HEAD

  17     regspec = [('INT', 'o', '0:63'),
  18                ('CR', 'cr_a', '0:3'),
  19                ('XER', 'xer_ca', '34,45'), # bit0: ca, bit1: ca32
  20                ('XER', 'xer_ov', '33,44'), # bit0: ov, bit1: ov32
  21                ('XER', 'xer_so', '32')]

hmmm i'm not seeing CA or CA32 in the output list.  going over the
page https://libre-soc.org/openpower/isa/fixedarith/ which comes from
the spec, that would seem to be the case (CA/CA32 not involved),
would you agree?

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