[libre-riscv-dev] TLB Replacement Policy
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Wed Apr 17 18:58:56 BST 2019
> > I was thinking of having a four way cache. Just mirroring what intel is
> currently doing as their TLB in my computer is 4-way with 64 entries and a
> single layer that is fully associative with 8 (I think). I think those are
> pretty reasonable numbers, what about you?
> > The conversion will definitely make it easier to implement on our end as
> I was having thoughts on how to store the required bits and they already
> did it so why change precedent.
> if you parameterise everything, we can always change it later.
Need to work out the name differences between existing code that you wrote
and ariane tlb and ptw. also decide what Bus Architecture to use.
Assoc Cache, how is that going?
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
More information about the libre-riscv-dev