[libre-riscv-dev] TLB Replacement Policy

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue Apr 16 06:53:39 BST 2019

On Mon, Apr 15, 2019 at 10:58 PM Daniel Benusovich
<flyingmonkeys1996 at gmail.com> wrote:
> It looks really good neat. Gj.

 cool.   i'll do some experiments with it, to sort-of make some unit tests.

> I spent the last couple of days looking over the other algorithms and also came to the conclusion that the psuedo LRU would probably be best for the cache. Which is neat to say the least.


> I was thinking of having a four way cache. Just mirroring what intel is currently doing as their TLB in my computer is 4-way with 64 entries and a single layer that is fully associative with 8  (I think). I think those are pretty reasonable numbers, what about you?
> The conversion will definitely make it easier to implement on our end as I was having thoughts on how to store the required bits and they already did it so why change precedent.

 if you parameterise everything, we can always change it later.


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