[libre-riscv-dev] TLB Replacement Policy

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Apr 18 06:15:24 BST 2019

(ccing the list again, hope that's ok daniel)

On Thu, Apr 18, 2019 at 4:15 AM Daniel Benusovich
<flyingmonkeys1996 at gmail.com> wrote:
> > Need to work out the name differences between existing code that you wrote and ariane tlb and ptw. also decide what Bus Architecture to use.
> I will take a look

 usual options are wishbone, AXI4, or more recently TileLink. wishbone
and AXI4 both have nmigen implementations around (and adapters in

TileLink is *really* complex, it was designed from the perspective of
Chisel3 and consequently requires OO programming techniques to be
deployed... if you implement it in pure verilog it's absolute hell,

AXI4 is apparently covered by patents... that should not necessarily
stop us from investigating it (even to the extent of working out if
the patents may be invalidated by researching to see if there is any
prior art - yes i'm serious! - or seeing if there is an organisation
that we can join that provides patent pool indemnification)

wishbone is entirely public domain.

basically, though, for a while, we can get away with not making a decision.

the integration however, if you look at ariane std_icache.v [1], the
caches are pulled into an AXI4 bus layout, the actual CPUs are
*slaves* - not Bus Masters - on the same AXI4 bus as the caches.

even minerva, which is a simple RV32 implementation, uses wishbone for
i-cache and LD/ST [2]

> > Assoc Cache, how is that going?
> Its alright I have had a cold the last few days so nothing on that
> front.

 no problem.

> By the end of the week I would like to finish implementing the
> psuedo LRU and have the assoc cache done with unit tests.

 cool.  i tried throwing some random experimentation values into the
ariane ptw... i have *no idea* what to expect... honestly whilst i can
handle straight code-translation, i feel you're better equipped to
determine if the results of a given unit test are actually correct.

> After that implement the cache into the TLB and start testing that guy.
> Sound like a plan?

 yeah :)


[1] https://github.com/pulp-platform/ariane/blob/master/src/cache_subsystem/std_icache.sv
[2] https://github.com/lambdaconcept/minerva/blob/master/minerva/units/loadstore.py#L9

More information about the libre-riscv-dev mailing list