[libre-riscv-dev] pipeline sync issues
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Tue Apr 16 10:55:15 BST 2019
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Tue, Apr 16, 2019 at 10:31 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
> On Mon, Apr 15, 2019 at 11:20 PM Jacob Lifshay <programmerjake at gmail.com>
> > I looked at the Queue class in Chisel's standard library, and it has a
> > ready/valid interface exactly equivalent to what I had written for the
> > ready/valid Stage API, except that Chisel uses the name "bits" instead of
> > "data" and Chisel splits the ready/valid interface into two types:
> > DecoupledIO and IrrevocableIO.
> > From what I can tell by reading the code, Queue with entries=1, pipe=true,
> > and flow=false is logically equivalent to RegStage and Queue with
> > entries=1, pipe=false, and flow=true is logically equivalent to
> > BreakReadyChainStage. I am translating Queue to nmigen to verify that
> > equivalence by comparing the Verilog output.
> I finished translating Queue and it appears to be an exact match for
> RegStage and an almost-exact match for BreakReadyChainStage, the only
> difference is the data register is loaded with a different value in don't
> care cases.
i thought something like that might happen, although it's hard to identify.
> The command I used is:
> python3 src/ChiselQueue.py generate -t il output.il && yosys
> <<<$'read_ilang output.il\nsynth\nabc -dff -g simple\nflatten\n;;;\nshow
> -format svg -prefix output -stretch'
> I attached the output svg
ah! excellent! line 95 tells me that "flow" is basically identical
in function to SyncFIFO's "fwft" (first word write through) parameter.
the important thing is, though, that rather than rely on the
characteristics of Memory (which in FPGAs do *not have write-through
capability*), the case where the queue is empty is *specifically
detected*, and the output made equal to the *incoming* data (in a
exxxxcelllent muahahahaah :)
also at line 51 i see you "solved" the problem of Memory not being
able to have only one entry... by creating a minimum 2-entry Memory
SRAM (then ignoring one of them!)
really, we should solve that properly by either:
* raising a bug/enhancement request for Memory to accept single-entry sizes
* creating a monkey-patch for nmigen that does exactly that
* write a special-case option for Queue that detects the case
"entries=1" and uses a Signal() instead of a Memory.
okay! so, i'll do some adaptation and throw it into the pot.
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