[libre-riscv-dev] pipeline sync issues
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Tue Apr 16 13:44:59 BST 2019
that's it: pipe mode is where the problems occur.
# set readable and writable (NOTE: see pipe mode below)
self.readable.eq(~empty), # cannot read if empty!
self.writable.eq(~full), # cannot write if full!
so that's all sensible, so far. if there's no room, don't allow
writing! unfortunately... "pipe mode" does this:
m.d.comb += self.writable.eq(1)
i.e. the "writeable" conditions are over-ridden (against plain
commonsense, i feel obliged to say).
thus, if read is enabled, writable is *FORCED* to be set. therefore,
if the output does NOT read the data, the input will DESTROY one value
in the FIFO by overwriting it.
that's why the unit tests that i wrote have been barfing when
BufferedPipeline has been connected to any of UnbufferedPipeline,
RegStage or BreakReadyStage, because they deliberately set/clear send
and receive conditions on a random basis.
so basically, pipe-mode requires - *REQUIRES* - that the down-stream
recipients read the damn data. if it says "read enabled", you MUST
read it, because the "pipe" has been set to a mode where new data
*will* come in.
would you concur, jacob?
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