[libre-riscv-dev] pipeline sync issues

Jacob Lifshay programmerjake at gmail.com
Tue Apr 16 10:04:28 BST 2019

On Mon, Apr 15, 2019 at 11:20 PM Jacob Lifshay <programmerjake at gmail.com>

> I looked at the Queue class in Chisel's standard library, and it has a
> ready/valid interface exactly equivalent to what I had written for the
> ready/valid Stage API, except that Chisel uses the name "bits" instead of
> "data" and Chisel splits the ready/valid interface into two types:
> DecoupledIO and IrrevocableIO.
> From what I can tell by reading the code, Queue with entries=1, pipe=true,
> and flow=false is logically equivalent to RegStage and Queue with
> entries=1, pipe=false, and flow=true is logically equivalent to
> BreakReadyChainStage. I am translating Queue to nmigen to verify that
> equivalence by comparing the Verilog output.
I finished translating Queue and it appears to be an exact match for
RegStage and an almost-exact match for BreakReadyChainStage, the only
difference is the data register is loaded with a different value in don't
care cases.

The command I used is:
python3 src/ChiselQueue.py generate -t il output.il && yosys
<<<$'read_ilang output.il\nsynth\nabc -dff -g simple\nflatten\n;;;\nshow
-format svg -prefix output -stretch'

I attached the output svg


Jacob Lifshay

More information about the libre-riscv-dev mailing list