[libre-riscv-dev] IEEE754 FPU turning into ALU with Reservation Stations

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Apr 13 06:25:54 BST 2019

On Sat, Apr 13, 2019 at 2:07 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> On Fri, Apr 12, 2019 at 9:18 PM Aleksandar Kostovic
> <alexandar.kostovic at gmail.com> wrote:
> > SO, i found this little gem:
> > http://verilogcodes.blogspot.com/2017/11/a-verilog-function-for-finding-square-root.html
> > This provides a "skeleton" which we can modify for floating point.
>  for-loops, blech! :)  yes it does.   excellent, go for it.

i read a bit of the paper that's linked, there, it's designed for
pipeline usage, which is nice, and apparently does not need a
multiplexor, which is nicer.

i don't understand it enough to be able to turn it into a 4-bit
variant, however we can do that with the trick of having two
*combinatorial* 2-bit stages linked together.

i added the c version to the comment string, to help understanding.


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