[libre-riscv-dev] pipeline stages controlling delays

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Apr 5 06:02:57 BST 2019

to support FSMs as pipeline stages (e.g. the FP div unit and others)
we will need a way for *stages* to signal that they are ready (or not)
to pass on or receive data.  i *think* that means that they need to be
able to override the PrevControl signals, by capturing and re-routing

that may - i think - be achieved transparently by having *two*
PrevControl instances in ControlBase, passing both of them to the
stage instance, and letting the stage instance make the decision about
how to proceed.

this currently ControlBase:

class ControlBase:
    def __init__(self, in_multi=None):
        self.p = PrevControl(in_multi)
        self.n = NextControl()

it would be modified to:
class ControlBase:
    def __init__(self, in_multi=None, stage_controls_ready=False):
        self.p = PrevControl(in_multi)
        self.n = NextControl()
        if stage_controls_ready:
            self.stage_p = PrevControl(in_multi)

and then the stage would have a function called say...
data_ready(self, p, stage_p) where an implementation would look like

def data_ready(self, m, p, stage_p):
     with m.If(stage_p.o_ready & self.stage_data_acceptance_conditions_right):

... it's more complicated than that, isn't it?  a similar re-routing
is needed on the n.o_valid, isn't it?  because the stage needs to be
able to indicate that its data is ready....

i'm trying to think of ways to minimise making the pipeline
implementation complex.


More information about the libre-riscv-dev mailing list