[libre-riscv-dev] pipeline stages controlling delays

Jacob Lifshay programmerjake at gmail.com
Fri Apr 5 06:06:29 BST 2019

On Thu, Apr 4, 2019, 22:04 Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> to support FSMs as pipeline stages (e.g. the FP div unit and others)
> we will need a way for *stages* to signal that they are ready (or not)
> to pass on or receive data.  i *think* that means that they need to be
> able to override the PrevControl signals, by capturing and re-routing
> them.
that's why I had put the control signals as members of Stage.

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