[libre-riscv-dev] IEEE754 FPU turning into ALU with Reservation Stations

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Apr 13 02:07:10 BST 2019

On Fri, Apr 12, 2019 at 9:18 PM Aleksandar Kostovic
<alexandar.kostovic at gmail.com> wrote:

> SO, i found this little gem:
> http://verilogcodes.blogspot.com/2017/11/a-verilog-function-for-finding-square-root.html
> This provides a "skeleton" which we can modify for floating point.

 for-loops, blech! :)  yes it does.   excellent, go for it.


More information about the libre-riscv-dev mailing list