[libre-riscv-dev] barrel processor as I/O and DMA controller
programmerjake at gmail.com
Wed Apr 10 18:29:44 BST 2019
Note that I don't think it would be particularly low power at 1GHz, so we
will want to run it at a lower clock rate most of the time.
On Wed, Apr 10, 2019, 10:27 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> On Wed, Apr 10, 2019 at 5:51 PM Jacob Lifshay <programmerjake at gmail.com>
> > I'd expect it to be able to get to 1GHz or so.
> fantastic. so, assuming say 4 time-slices, that's 250mhz per
> time-slice, that would leave 5 instructions per clock cycle with which
> to do data transfers @ say 50mhz.
> if that is achievable it would mean that we could do e.g. eMMC in
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