[libre-riscv-dev] barrel processor as I/O and DMA controller

[Luke Kenneth Casson Leighton]

On Wed, Apr 10, 2019 at 5:51 PM Jacob Lifshay <programmerjake at gmail.com> wrote:
>
> I'd expect it to be able to get to 1GHz or so.

 fantastic.  so, assuming say 4 time-slices, that's 250mhz per
time-slice, that would leave 5 instructions per clock cycle with which
to do data transfers @ say 50mhz.

 if that is achievable it would mean that we could do e.g. eMMC in software.

l.