[libre-riscv-dev] barrel processor as I/O and DMA controller
programmerjake at gmail.com
Wed Apr 10 17:51:28 BST 2019
I'd expect it to be able to get to 1GHz or so.
On Wed, Apr 10, 2019, 04:38 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> jacob, hi,
> do you think the 5-stage design you're working on could hit the same
> 800mhz target clock rate in 40 to 28nm? the reason i ask is, it would
> theoretically do double-duty as a DMA controller.
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> libre-riscv-dev at lists.libre-riscv.org
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