[libre-riscv-dev] barrel processor as I/O and DMA controller

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Apr 10 12:37:06 BST 2019

jacob, hi,

do you think the 5-stage design you're working on could hit the same
800mhz target clock rate in 40 to 28nm?  the reason i ask is, it would
theoretically do double-duty as a DMA controller.


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