[libre-riscv-dev] pipeline stages controlling delays

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Apr 6 10:56:48 BST 2019

On Sat, Apr 6, 2019 at 5:39 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> jacob could you take a look at test999, it's extremely odd.  i guessed
> that there might be a bug in UnbufferedPipeline's logic so i copied
> the logic from BreakReadyChainStage, which basically stores the
> _output_ rather than the input, plus data_valid is the logic-inverse
> of buffer_full.

 got it.... i don't know how to fix it: p_o_ready is combinatorial and
is an entire cycle *too early*, relative to the data.

 so the BufferedPipeline is receiving a n_i_ready signal indicating
that the next stage (the UnbufferedPipeline) is ready when it is not.

 the *other way round* is fine... because there is a delay introduced.

 really needs properly investigating, i'm out of my depth here.


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