[libre-riscv-dev] pipeline stages controlling delays

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Apr 6 12:30:28 BST 2019

moo?  i took a complete random guess that if i stripped the register
r_data out of BufferedPipeline (or, at least, made its use optional),
the result would be a data control logic block where its ready/valid
signals were synchronised with the data.

this total random guess at which bits of the logic to switch off with
a python parameter turned out to work.

it needs investigating, what the difference is: basically, the
p_o_ready not being synchronous with the data in UnbufferedPipeline is
what's causing things to go wrong.  it's still useful: it's just not
possible to chain it with a BufferedPipeline (not afterwards, at
least).  one thought there is to simply raise an assert if that's

so this leaves investigating the d_valid / d_ready bug.


More information about the libre-riscv-dev mailing list