[libre-riscv-dev] pipeline stages controlling delays

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Apr 6 05:39:18 BST 2019

jacob could you take a look at test999, it's extremely odd.  i guessed
that there might be a bug in UnbufferedPipeline's logic so i copied
the logic from BreakReadyChainStage, which basically stores the
_output_ rather than the input, plus data_valid is the logic-inverse
of buffer_full.

it didn't help.

the bug is that a 2-stage pipeline comprising:

* a BufferedPipeline followed by
* an UnbufferedPipeline (or UnbufferedPipeline2 which is the logic
from BreakReadyChainStage)

will FAIL for no good reason that i can see.

*all other permutations work fine*.

* BufferedPipeline followed by BufferedPipeline: fine
* UnBufferedPipeline followed by BufferedPipeline: fine
* UnBufferedPipeline2 followed by BufferedPipeline: fine
* UnBufferedPipeline followed by UnbufferedPipeline: fine
* UnBufferedPipeline2 followed by UnbufferedPipeline2: fine

i haven't tried permutations of UnbufferedPipeline with UnbufferedPipeline2.

this bug occurred *before* the addition of the dynamic data
valid/ready logic, i just hadn't written a unit test that caused the
above failure until writing the dynamic data valid/ready code.  as it
was interfering with the development i went back to a version of the
code from a day ago, and *confirmed* that the bug is still present
*before* the dynamic data valid/ready logic was added.


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