[libre-riscv-dev] simple barrel processor pipeline design diagram

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Apr 3 06:50:34 BST 2019

On Wed, Apr 3, 2019 at 6:41 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
> I created a pipeline design diagram for the simple barrel processor I'm
> creating to familiarize myself with nmigen and to possibly use as a
> low-power minion core. I'm planning on it supporting RV64IMAC. It has a
> 5-stage pipeline, so supports 5 harts.
> https://salsa.debian.org/Kazan-team/simple-barrel-processor/blob/master/doc/PipelineDesign.svg

 i love it!  i love the way everything's connected together.  it
should be really easy to implement that, and it helps understand
what's going on.

question: is it necessary to have RS1 and RS2 be in different stages?
if the regfile is 2R1W it should be able to handle 2 simultaneous
reads, RS1 and RS2.  or, is that done just to be able to get 5 cycles?


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