[libre-riscv-dev] simple barrel processor pipeline design diagram
programmerjake at gmail.com
Wed Apr 3 07:24:33 BST 2019
On Tue, Apr 2, 2019 at 10:51 PM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> On Wed, Apr 3, 2019 at 6:41 AM Jacob Lifshay <programmerjake at gmail.com>
> > I created a pipeline design diagram for the simple barrel processor I'm
> > creating to familiarize myself with nmigen and to possibly use as a
> > low-power minion core. I'm planning on it supporting RV64IMAC. It has a
> > 5-stage pipeline, so supports 5 harts.
> i love it! i love the way everything's connected together.
> should be really easy to implement that, and it helps understand
> what's going on.
> question: is it necessary to have RS1 and RS2 be in different stages?
> if the regfile is 2R1W it should be able to handle 2 simultaneous
> reads, RS1 and RS2. or, is that done just to be able to get 5 cycles?
It's done to allow regfile to be split into 5 separate banks, each bank has
a single read/write port. If both reads were done in the same cycle, then
the regfile banks would need to be dual-ported (increasing area and power
by a lot).
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