[Libre-soc-isa] [Bug 697] SVP64 Reduce Modes

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=697

--- Comment #31 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
00      0       dz sz   normal mode
00      1       0 RG    scalar reduce mode (mapreduce), SUBVL=1
00      1       1 /     parallel reduce mode (mapreduce), SUBVL=1
00      1       SVM RG  subvector reduce mode, SUBVL>1

add:

00      1       1 0     parallel reduce mode (mapreduce), SUBVL=1
00      1       1 1     scalar relative reduce mode

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