[Libre-soc-isa] [Bug 697] SVP64 Reduce Modes

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed May 18 18:53:55 BST 2022


--- Comment #30 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
something along these lines:

* RB-RA (the register *numbers* not GPR(RB)-GPR(RA) is computed and stored,
  call it offs
* RT-RA likewise call it roffs
* a sequence of offsets is computed from the predicate mask
  0b1001101 would create indices [0, 2, 3, 6], call it idxs

the for-loop therefore goes:

   for i in range(len(idxs)-MAX(roffs, offs)):
      ra = RA + idxs[i]
      rb = RA + idxs[i+offs]
      result = OPERATION(GPR(ra), GPR(rb))
      rt = RA + idxs[i+roffs]
      GPR(rt) = result

taking twin-predication into account would involve using the dest
predicate to create a separate list of indices.

if RT != RA then this could be used to e.g. create a vector sequence of
differences but e.g. skip certain elements.

if RT == RA then as usual for mr and mr/RG (reverse gear) mode this becomes
a cumulative sum.

if RT<RA then the first few starting elements are skipped to always make
sure idxs[] referencing is within range

the bit that's conceptually new is that the actual register numbers are
from the difference to RA as a baseline register.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the Libre-SOC-ISA mailing list