[Libre-soc-isa] [Bug 697] SVP64 Reduce Modes

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=697

--- Comment #29 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
drat.

when looking at viota i realised that for scalar reduction
when predicate masks are involved everything goes to hell.
the current definition of scalar reduction is one that
disables "stopping" on SV loops if the destination is a
scalar because the destination can be used as an accumulator

    sv.add/mr r0, r3.v, r0

this will use r0 as a scalar accumulator

    sv.madd/mr r0, r8.v, r16.v, r0

this is basically dotproduct.

a prefix-sum (fibonacci) can be done as:

    sv.addi/mr r1.v, r1.v, r2.v, 1

but - and this is the problem - if predication is enabled on
that sv.addi it all goes to hell.

first question: can a useful schedule be created which skips over
masked-out elements

second question: can the registers be easily determined (which one
is the accumulator)

third question: are there enough bits in MODE to include this.

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