[Libre-soc-dev] maybe buy fpga for adding to our ci server

[lkcl]

On April 6, 2022 3:21:29 PM UTC, Jacob Lifshay <programmerjake at gmail.com> wrote:
>On Wed, Apr 6, 2022, 03:30 lkcl <luke.leighton at gmail.com> wrote:
>
>> On Wed, Apr 6, 2022 at 12:02 AM Jacob Lifshay
><programmerjake at gmail.com>
>> wrote:
>> > orangecrab can do usb serial emulation...
>>
>> that means that someone has to spend the time writing a USB port,
>> because after having been treated so abusively by the lead developer
>> of litex i'm not letting litex source code onto the server
>
>
>didn't realize valentyusb was litex...

it's mostly migen with a little bit litex
https://github.com/im-tomu/valentyusb/blob/master/valentyusb/usbcore/cpu/usbwishboneburstbridge.py

which means at some point removing litex and using valentyusb standalone (or converted to nmigen) is doable.

the only thing being, USB is quite... hairy.  as in, BIG. setting up the drivers (endpoints) is something of a pain in the ass.

i created a USB 1.1 Keyboard with an STM32F years ago: setting up the endpoint map took several days research. 

>k, sounds good, though I'll probably want to wire it to the build
>server's
>internal rs232 port instead (iirc it's a header on the motherboard --
>can
>easily build the required level-shifting)...why waste a perfectly good
>serial port? 

because if you break it, that's really expensive.  FT232 USBUARTs on the other hand are cheap.


> also allows me to put the fpga inside the server's case
>which
>is important for protection from stuff accidentally falling on
>it...it's in
>the corner of my bedroom.

i'm reasonably certain you should find the USB sockets on the front panel will be detachable from the case.

you should then be able to also put the OC inside as well.

l.