[Libre-soc-dev] LibreSOC Implementation on arty7 fpga dev boards.

[varun mohan]

> "make ls180_verilog"
Is this the same for targeting FPGAs..??

Varun

On Wed, Oct 13, 2021 at 3:38 PM lkcl <luke.leighton at gmail.com> wrote:

> On Wed, Oct 13, 2021 at 6:10 AM varun mohan <varunmadhavam at gmail.com>
> wrote:
> >
> > > have no idea, you'll have to research the project, find its homepage,
> > > and read their developer instructions.
> > Okey. Will explore.
>
> also, reminder, update nmigen and try using the symbiflow version of yosys.
>
> > I could only find one issuer_verilog.py in all the repos so using the
> below command to generate the ibresoc.v file
> >
> > python3 /opt/libresoc/soc/src/soc/simple/issuer_verilog.py libresoc.v
> >
> > Is this the correct approach..!?
>
>
> https://git.libre-soc.org/?p=soc.git;a=blob;f=Makefile;h=3d4ea62db5a779f896d1f59665014783681f0523;hb=dd84c610a68a556eb532cee133df68c4354dbf32#l47
>
> "make ls180_verilog"
>
> there are many build options.  you've set the default options with the
> above command.
>
> l.
>