[Libre-soc-dev] LibreSOC Implementation on arty7 fpga dev boards.
luke.leighton at gmail.com
Wed Oct 13 11:08:25 BST 2021
On Wed, Oct 13, 2021 at 6:10 AM varun mohan <varunmadhavam at gmail.com> wrote:
> > have no idea, you'll have to research the project, find its homepage,
> > and read their developer instructions.
> Okey. Will explore.
also, reminder, update nmigen and try using the symbiflow version of yosys.
> I could only find one issuer_verilog.py in all the repos so using the below command to generate the ibresoc.v file
> python3 /opt/libresoc/soc/src/soc/simple/issuer_verilog.py libresoc.v
> Is this the correct approach..!?
there are many build options. you've set the default options with the
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