[Libre-soc-dev] LibreSOC Implementation on arty7 fpga dev boards.

[varun mohan]

 > have no idea, you'll have to research the project, find its homepage,
> and read their developer instructions.
Okey. Will explore.

I have a doubt. While using the lbresoc-litex repo, its depends on a file
"libresoc.v" in the libresoc directory. Going through the makefiles and
readme files, I figured out that this has to be created by executing a
python script called issuer_verilog.py.
I could only find one issuer_verilog.py in all the repos so using the below
command to generate the ibresoc.v file

python3 /opt/libresoc/soc/src/soc/simple/issuer_verilog.py libresoc.v

Is this the correct approach..!?

Regards
Varun

On Sun, Oct 10, 2021 at 6:26 PM lkcl <luke.leighton at gmail.com> wrote:

> On Sun, Oct 10, 2021 at 12:47 PM varun mohan <varunmadhavam at gmail.com>
> wrote:
> >
> > > ahh, excellent: now you are free and clear to report it upstream with
> the vpr developers.
> >
> > How do I do this exactly..!..Create an issue in the github repo or
> something else..!!!?
>
> i have no idea, you'll have to research the project, find its homepage,
> and read their developer instructions.
>
> l.
>