[Libre-soc-dev] LibreSOC Implementation on arty7 fpga dev boards.

[lkcl]

On Wed, Oct 13, 2021 at 1:33 PM varun mohan <varunmadhavam at gmail.com> wrote:
>
> > "make ls180_verilog"
> Is this the same for targeting FPGAs..??

yyeah... effectively.  although that version doesn't request 4k SRAMs

perhaps try the version with no pll as well.  line 41

https://git.libre-soc.org/?p=soc.git;a=blob;f=Makefile;h=3d4ea62db5a779f896d1f59665014783681f0523;hb=dd84c610a68a556eb532cee133df68c4354dbf32#l41

you just have to see how it goes: at the bare minimum use the
"--disable-svp64" option.

l.