[Libre-soc-dev] LibreSOC Implementation on arty7 fpga dev boards.
luke.leighton at gmail.com
Wed Oct 13 13:51:44 BST 2021
On Wed, Oct 13, 2021 at 1:33 PM varun mohan <varunmadhavam at gmail.com> wrote:
> > "make ls180_verilog"
> Is this the same for targeting FPGAs..??
yyeah... effectively. although that version doesn't request 4k SRAMs
perhaps try the version with no pll as well. line 41
you just have to see how it goes: at the bare minimum use the
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