[Libre-soc-dev] LibreSOC Implementation on arty7 fpga dev boards.

[varun mohan]

OK. So tried as you suggested, but still the same error.

ERROR: Conflicting init values for signal 1'0
(\test_issuer.ti.jtag.dmi0_datasr_update_core = 1'0 != 1'x).

I am now doing all the steps from the beginning again just to ensure that I
have not done any damage during my experimentation.
Just to confirm once, Litex has to be installed as mentioned in the
original litex repo right..!?..specifically by executing the command
"./litex_setup.py init install --user" right..!?
One more thing, in this link https://libre-soc.org/HDL_workflow/devscripts/
you are installing the python dev repos as root user. Is it necessary...??

Regards
Varun

On Wed, Oct 6, 2021 at 9:13 PM lkcl <luke.leighton at gmail.com> wrote:

>
>
> On October 6, 2021 2:49:31 PM UTC, varun mohan <varunmadhavam at gmail.com>
> wrote:
> >> varun please take care to always reply to the list.  always hit
> >"reply
> >all".
> >I am sorry, will take care here after.
> >
> >> i said, the version you already had was ok (in the list)
> >my mail was sent before i read your last mail on the subject but I
> >guess
> >you are talking about the litex repo.
>
> no, i am referring to the list in the bugreport.
>
> if you deviated from that list you should not have done so and we already
> checked it was completely unnecesary to deviate from that list.
>
> > What about the litex_boards repo.
> >The
> >commits I mentioned in the mail were for that repo.
>
> check the list.  use the commits in the list and no other commits.
>
> this ensures we are "on the same page" and so any problems that occur we
> do not first have to go "ok so what commit for this repo, what commit for
> that repo" etc etc
>
> >> a7-a35t.  you've not passed the correct a7-a100t argument but that
> >can be
> >dealt with later.
> >I passed a7-35t on purpose, is it not supported..!?
>
> ahh ok.
>
> well, you *might* be lucky and have enough resources.  ls180 needs around
> 20k LUT4s.  you have only 35k.  it should just about fit, without symbiflow
> freaking out.
>
> nextpnr-ecp5 *really* struggles if you get within 50% of available
> resources.  an a7-100t would have kept you away from potential issues
> there, but let's see what happens.
>
> at least you are running symbiflow successfully niw, which is good.
>
> >
> >> this is because you have the wrong version of yosys for nmigen to
> >work
> >with.
> >
> >> check again the wiki page i sent 12 hours ago and use the yosys
> >version
> >from that.
> >
> >I Totally forgot about this.
>
> doh :)
>
> it is rather unfortunate, free software they keep moving and "fixing"
> things without regard for backwards compatibility.
>
>
>
> > Will check and revert. I have an exam
> >tomorrow. So probably after that.
>
> ok good luck keep us informed.  i would love to run this as well but have
> to prepare the lecture on FPGA-ASIC differences.
>
> l.
>