[Libre-soc-dev] LibreSOC Implementation on arty7 fpga dev boards.

lkcl luke.leighton at gmail.com
Wed Oct 6 16:43:38 BST 2021

On October 6, 2021 2:49:31 PM UTC, varun mohan <varunmadhavam at gmail.com> wrote:
>> varun please take care to always reply to the list.  always hit
>I am sorry, will take care here after.
>> i said, the version you already had was ok (in the list)
>my mail was sent before i read your last mail on the subject but I
>you are talking about the litex repo.

no, i am referring to the list in the bugreport.

if you deviated from that list you should not have done so and we already checked it was completely unnecesary to deviate from that list.

> What about the litex_boards repo.
>commits I mentioned in the mail were for that repo.

check the list.  use the commits in the list and no other commits.

this ensures we are "on the same page" and so any problems that occur we do not first have to go "ok so what commit for this repo, what commit for that repo" etc etc

>> a7-a35t.  you've not passed the correct a7-a100t argument but that
>can be
>dealt with later.
>I passed a7-35t on purpose, is it not supported..!?

ahh ok.

well, you *might* be lucky and have enough resources.  ls180 needs around 20k LUT4s.  you have only 35k.  it should just about fit, without symbiflow freaking out.

nextpnr-ecp5 *really* struggles if you get within 50% of available resources.  an a7-100t would have kept you away from potential issues there, but let's see what happens.

at least you are running symbiflow successfully niw, which is good.

>> this is because you have the wrong version of yosys for nmigen to
>> check again the wiki page i sent 12 hours ago and use the yosys
>from that.
>I Totally forgot about this.

doh :)

it is rather unfortunate, free software they keep moving and "fixing" things without regard for backwards compatibility.

> Will check and revert. I have an exam
>tomorrow. So probably after that.

ok good luck keep us informed.  i would love to run this as well but have to prepare the lecture on FPGA-ASIC differences.


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