[Libre-soc-dev] adding an extra field to sv_analysys.py output (out2)

[Luke Kenneth Casson Leighton]

we've a situation where, from following microwatt decode1.vhdl format,
there is no "out2" register column.  some register information, rather
than being in the VHDL files / CSV files, was still done by hand.

we followed that... somewhat:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_decoder2.py;h=3813295c5142786202bca8c2f220ecd0d246a179;hb=1ebec3c8d403a74a495d317d9c722aa4243bd279#l411

this is where, rather than there being a column that identifies the
2nd output, it's detected "is LDST update mode set", which to be
honest is probably more gate-efficient but also a damn nuisance.

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_decoder2.py;h=3813295c5142786202bca8c2f220ecd0d246a179;hb=1ebec3c8d403a74a495d317d9c722aa4243bd279#l1185

here, we again follow what microwatt does, and really shouldn't.

however the advantages of being closer to what microwatt does outweigh
the disadvantages.... except when we're auto-generating code for
adding SVP64 to microwatt.

to that end what i'm going to do is add an extra column to the RM
(SVP64) output CSV files, called "out2".  i'm not going to alter the
v3.0B CSV files themselves: one other idea is to change the get_csv
function to *add* that column (based on "if upd == LDSTMode.update").

the reason is because this column is missing:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_decoder2.py;h=3813295c5142786202bca8c2f220ecd0d246a179;hb=1ebec3c8d403a74a495d317d9c722aa4243bd279#l1089

consequently we can't properly decode SVP64 EXTRA2/3 for the 2nd
output register.

l.

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