[Libre-soc-dev] scalar instructions and SVP64

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Mar 10 19:53:09 GMT 2021

On Wednesday, March 10, 2021, Jacob Lifshay <programmerjake at gmail.com>

> I'd expect the additional gate cost to be on the order of 10 gates in the
> decoder and 20-30 gates in the VL-loop stage (which I'm assuming comes
> after the decoder).

no!  please see the test issuer source code and discussions which have been
ongoing for several weeks now.

the instruction decoder is *after* the VL identification because VL is part
of the same state including SVSTATE MSR and PC.

the instruction is *not* decoded - at all - at the point where SVP64 has
been identified.

PowerDecoder2 is 4,000+ gates and is so big it has to be divided into 2
separate pipeline stages (12 individual satellite decoders one per pipeline)

that 4,000 gates is a massive long mux cascade where it is COMPLETELY
unacceptable to make anything critically depend on it.

and everything that you suggest due to this fundamental misunderstanding of
what SV is categorically requires exactly that.

therefore the answer is and will always remain "no".


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