[Libre-soc-dev] scalar instructions and SVP64

[Jacob Lifshay]

On Wed, Mar 10, 2021, 11:20 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> jacob i suspect what has happened is that gmail has marked messages as read
> without your consent and knowledge.  it did this to me and i saw neither
> hendrik nor adam's message until i reviewee the archives.
>
> could you go back and check because i wrote a comprehensive description of
> how the hardware will be performance compromised yet only 30 minutes ago
> you advocated exactly such a compromised idea.
>

I saw that, I wrote in my email exactly how the hardware won't have an
issue for the fetch/decode/VL-loop pipe because what I described (not the
speculative issue then cancel paragraph) shows exactly how the decoder
won't need additional pipeline stages:
I'd expect the additional gate cost to be on the order of 10 gates in the
decoder and 20-30 gates in the VL-loop stage (which I'm assuming comes
after the decoder). It should add 1-2 gate delays to the last decode stage
if on the critical path (unlikely), otherwise 0 delay. Depending on
implementation strategy, it should add 1-2 gate delays to the VL-loop
stage, which I expect to not have tight timing due to it being mostly just
muxes.

Also, remember that the overall scalar/vector is an output of the decoder,
none of the rest of the decoder needs to know/care what value it has, so it
can be easily decoded in parallel with the rest of the instruction -- not
serially like you feared.

Jacob