[Libre-soc-dev] Regarding LibreSoC build and OS booting medium

Nalluri sasi Kiran kiransasinalluri at gmail.com
Mon Jun 28 14:22:45 BST 2021

Hi all,

I am sasi kiran. I wanted to build an SoC using microwatt and LibreSoC. I
had run some files. Now i am getting some OS issues.
In some header file there is a define "CSR_UART_BASE"
In the main.c file  it enters into line serial boot() from boot_sequence().
>From there I am getting a timeout error.
I couldn't understand what's wrong.I am attaching some screenshots.Kindly
take a look.

Thank you "Luke Kenneth Casson Leighton and Ganesan Narayanasamy" for all
the help and guidance during the build.

[spdeeprom] loaded (addr = 0x0)
[serial2console] loaded (0x561dc4ea4190)
[ethernet] loaded (0x561dc4ea4190)
[clocker] loaded
[xgmii_ethernet] loaded (0x561dc4ea4190)
[serial2tcp] loaded (0x561dc4ea4190)
[clocker] sys_clk: freq_hz=1000000, phase_deg=0
/home/root/litex/litex/build/sim/core/sim.c:95 Could not find module

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
   Build your hardware, easily!

 (c) Copyright 2012-2021 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS CRC passed (0c8307c2)

 Migen git sha1: 3ffd64c
 LiteX git sha1: 23afca3d

--=============== SoC ==================--
CPU: Libre-SoC @ 100MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 8-bit data
ROM: 64KiB
SRAM: 256KiB
L2: 0KiB
SDRAM: 32768KiB 16-bit @ 100MT/s (CL-2 CWL-2)

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x00000040000000 (8B)...
  Write: 0x40000000-0x40000008 8B
   Read: 0x40000000-0x40000008 8B
Memtest OK
Memspeed at 0x00000040000000 (8B)...
  Write speed: 1022.5KiB/s
   Read speed: 1.0MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely
No boot medium found

--============= Console ================--

More information about the Libre-soc-dev mailing list