[Libre-soc-dev] Question about some "empty" components in the design

[Luke Kenneth Casson Leighton]

Jean-Paul the nets are correctly being merged...

        + rdpick_CR_cr_b [.model]
Reading .inputs of &<id:91234 Cell rdpick_CR_cr_b>
rdpick_CR_cr_b net create:1 &<id:91237 Net "i" e-- LOGICAL i--- (IN)>
Reading .inputs of &<id:91234 Cell rdpick_CR_cr_b> DONE
Reading .outputs of &<id:91234 Cell rdpick_CR_cr_b>
rdpick_CR_cr_b net create:2 &<id:91238 Net "o" e-- LOGICAL -o-- (OUT)>
rdpick_CR_cr_b net create:2 &<id:91239 Net "en_o" e-- LOGICAL -o-- (OUT)>
Reading .outputs of &<id:91234 Cell rdpick_CR_cr_b> DONE
rdpick_CR_cr_b alias net merge:&<id:91239 Net "en_o" e-- LOGICAL -o--
(OUT)> -> &<id:91237 Net "i" e-- LOGICAL i--- (IN)>
rdpick_CR_cr_b alias net merge:&<id:91238 Net "o" e-- LOGICAL -o--
(OUT)> -> &<id:91237 Net "i" e-- LOGICAL i--- (IN)>

... the consequences are that there's nothing
actually using or connecting them.

hmmm  i THINK it might be okay.  this is back in cmpt_core.vst:

  subckt_4051_a4_x2 : a4_x2
  port map ( i0  => fus_cu_rd_rel_o_33(4)
           , i1  => abc_485251_new_n6930
           , i2  => core_cr_in2_ok
           , i3  => core_core_fn_unit(6)
           , q   => rdpick_curu_cr_b_o
           , vdd => vdd
           , vss => vss
           );

according to the BLIF file that should be q => rdpick_curu_cr_b_i

but thanks to the aliases generated frm net merge above, it's
been *renamed* - correctly - to rdpick_curu_cr_b_o

so i think we're good.  it's very strange, but ok.

l.