[Libre-soc-dev] Question about some "empty" components in the design

[Luke Kenneth Casson Leighton]

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Mon, Jun 28, 2021 at 10:42 AM Marie-Minerve Louerat
<Marie-Minerve.Louerat at lip6.fr> wrote:
>
> Hello,
>
> While doing the Layout Versus Schematic check of the whole design,
>
> I found these  components which do not instantiate anything:
>
>   cmpt_dummy.vst
>   cmpt_rdpick_curu_cr_b.vst
>   cmpt_rdpick_curu_cr_c.vst
>   cmpt_rdpick_curu_full_cr.vst
>   cmpt_rdpick_supuru_spr1.vst
>   cmpt_rdpick_xueuru_xer_ov.vst
>   cmpt_wrpick_curu_full_cr.vst
>   cmpt_wrpick_supuru_spr1.vst
>   cmpt_wrpick_sutuautueu_msr.vst
>   cmpt_wrpick_sutuautueu_svstate.vst
>
>
> They have just the interface with terminals.
>
> Is that a problem or not?

the verilog reduces to this:
module rdpick_CR_cr_b(o, en_o, i);
  wire \$3 ;
  output en_o;
  input i;
  output o;
  wire t0;
  assign \$3  = i;
  assign en_o = i;
  assign o = i;
  assign t0 = i;
endmodule

which in turn is simply connecting input to output:

# Generated by Yosys 0.9+4052 (git sha1 a58571d0, clang 9.0.1-12 -fPIC -Os)

.model rdpick_CR_cr_b
.inputs i
.outputs o en_o
.names $false
.names $true
1
.names $undef
.names i t0
1 1
.names i o
1 1
.names i en_o
1 1
.names i \$3
1 1
.end

however the VST file is empty, it is NOT connecting input to output:

entity cmpt_rdpick_cr_cr_b is
  port ( i   : in bit
       ; vdd : linkage bit
       ; vss : linkage bit
       );
end cmpt_rdpick_cr_cr_b;

architecture structural of cmpt_rdpick_cr_cr_b is
begin
end structural;

it has DELETED the outputs which are meant to be connected directly to
the inputs.

so yes, it's an error that needs fixing.

l.