[Libre-soc-dev] Regarding LibreSoC build and OS booting medium
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Mon Jun 28 14:48:01 BST 2021
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Mon, Jun 28, 2021 at 2:23 PM Nalluri sasi Kiran
<kiransasinalluri at gmail.com> wrote:
> Hi all,
> I am sasi kiran.
hi Sasi, welcome
> I wanted to build an SoC using microwatt and LibreSoC.
> had run some files. Now i am getting some OS issues.
> In some header file there is a define "CSR_UART_BASE"
> In the main.c file it enters into line serial boot() from boot_sequence().
> From there I am getting a timeout error.
this is correct behaviour for the BIOS. normally, if uploaded to an FPGA,
you would connect a script to the USB-UART and use it to upload
a program directly into memory.
in _theory_ you could connect the same program to the sim.py console?
(using unix "pipe"). however i have never done it.
basically, you've correctly demonstrated that the BIOS is working,
which in turn demonstrates that the sim.py is working.
now, if you want to connect to sim.py with openocd, you can,
see this README:
although it is designed for VERSA ECP5 the *exact same command
works on sim.py* but you must patch litex, first. see below "jtagremote"
> I couldn't understand what's wrong.
nothing's wrong, it's functioning perfectly correctly.
now, if you want to, you can see in sim.py that you can uncomment
some of the binary files (helloworld.bin, xics.bin) for which you'll
need microwatt checked out, and you can run those.
it's not perfect, but it's functional. if you want to help tidy it up
you are more than welcome.
> Thank you "Luke Kenneth Casson Leighton and Ganesan Narayanasamy" for all
> the help and guidance during the build.
no problem. do help out anyone else with the same question, ok?
> [spdeeprom] loaded (addr = 0x0)
> [serial2console] loaded (0x561dc4ea4190)
> [ethernet] loaded (0x561dc4ea4190)
> [clocker] loaded
> [xgmii_ethernet] loaded (0x561dc4ea4190)
> [serial2tcp] loaded (0x561dc4ea4190)
> [clocker] sys_clk: freq_hz=1000000, phase_deg=0
> /home/root/litex/litex/build/sim/core/sim.c:95 Could not find module
... ok here. this you will need to look in the *litex* source
add "jtagremote" to that, and recompile by running sim.py
then, you will find that the openocd command will successfully connect.
it's *VERY* basic - you can only send raw JTAG commands.
there is more that you can do, but get that working first, ok?
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