[Libre-soc-dev] Questions about the logos.
Jean-Paul.Chaput at lip6.fr
Tue Jun 15 12:01:04 BST 2021
On Tue, 2021-06-15 at 11:05 +0100, Luke Kenneth Casson Leighton wrote:
> crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
> On Tue, Jun 15, 2021 at 10:50 AM Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>
> > Hello Staf,
> > As said in the title, I have some questions about including
> > the logo:
> > 1. The GDS do not contains the logo drawn in the top metal layer,
> > but also all the other metals. I assume it is for density reasons.
> > 2. In additions to those layers, there is a layer Id 150, with
> > DATATYPE 1 to 6. What are they for? I
> blockage, i presume? which layer number is that supposed to be?
Could not tell you which number it is (NDA :-( ), but I have it
and it is not 150...
> f they need to be included,
> > we must create an associated basic layers in techno.py.
> > 3. Where do I put the logos on the chip.
> bottom left
> They are all around 150um
> > wide, and that do not fit in the spare triangular area in the
> > pads corners.
> they need to be actually visible under a microscope for TSMC's
> people to get the orientation correct - by hand - when putting into
> the package.
We can assume that, as they need to see the bounding area of the
pads, a size close to it is big enough. So, one square logo of
50nm side would perfectly fit.
> thus i suspect they will actually all need to be dropped into the
> *main* area.
I don't like putting logos in the main area, they will complicate
the work of the P&R and can be source of errors.
Maybe I can put them, in METAL6 only, between the power lines.
Same restriction : no more than 50um wide.
.-. J e a n - P a u l C h a p u t / Administrateur Systeme
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