[Libre-soc-dev] Questions about the logos.

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue Jun 15 11:05:46 BST 2021

crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Tue, Jun 15, 2021 at 10:50 AM Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>

> Hello Staf,
> As said in the title, I have some questions about including
> the logo:
> 1. The GDS do not contains the logo drawn in the top metal layer,
>    but also all the other metals. I assume it is for density reasons.
> 2. In additions to those layers, there is a layer Id 150, with
>    DATATYPE 1 to 6. What are they for? I

blockage, i presume?  which layer number is that supposed to be?

f they need to be included,
>    we must create an associated basic layers in techno.py.
> 3. Where do I put the logos on the chip.

bottom left

They are all around 150um
>    wide, and that do not fit in the spare triangular area in the
>    pads corners.

they need to be actually visible under a microscope for TSMC's
people to get the orientation correct - by hand - when putting into
the package.

thus i suspect they will actually all need to be dropped into the
*main* area.

hence the blockage nets.



More information about the Libre-soc-dev mailing list