[Libre-soc-dev] Unexpected clock connexions.

[Luke Kenneth Casson Leighton]

---
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On Sat, Jun 5, 2021 at 1:41 PM Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>
wrote:

> On Sat, 2021-06-05 at 13:17 +0100, Luke Kenneth Casson Leighton wrote:
> > i've added the dummy (fake) PLL to experiments10_verilog using nsxlib
> with
> > the (fake) PLL cell
> >
> https://git.libre-soc.org/?p=soclayout.git;a=commitdiff;h=a876c5dd61a53230de74b2ca2900e0e09490da95
> >
> > also worked out how to fix the nsxlib error "jtag_tck_from_pad" is not a
> > clock tree error
> >
> https://git.libre-soc.org/?p=soclayout.git;a=commitdiff;h=c24e13b1078fa2d358d6b7f91cfd96905c100769
> >
> > i am however experimenting tracking down the right H-Tree clock for use
> in
> > ls180Conf, it's probably
> >
> >     ls180Conf.useHTree('por_clk)
> >
> > not
> >
> >     ls180Conf.useHTree('core.por_clk')
>
>   Nono. That's correct. It is really 'core.por_clk'.
>

ok - except this is not a signal that exists.  also it is not helping that
there is
a component (test_issuer.ti.core) named "core", however as that is further
down the hierarchy it's not encountered, here, with this search.


>     "representative" at corona level, we must reach it through
>     the path : 'core.por_clk' (path rooted in corona model,
>     one instance 'core', which is the ls180).
>

doesn't exist.  you *might* mean pllclk_clk, which is the output
from the PLL

> also, is it likely that "coresync_rst" also has to be added?
>
>   Depends. It is in the "middle range". Many sinks, but maybe
>   not that much to need an H-Tree. If it needs a low skew, maybe.
>

it might be possible to get away with running a reset and set the
processor to "STOP" mode.

wait for a bit...

then bring the processor out of "STOP" mode.

i think this is what all JTAG unit tests do anyway.

as long as the processor is held in "STOP" whilst reset is being
run, it'll be fine.

l.